1. FIELD OF THE INVENTION
This invention relates in general to comparator circuits, and in particular, to a comparator circuit adapted for use in a metal-oxide-semiconductor (MOS) analog-to-digital (A/D) converter circuit.
2. DESCRIPTION OF THE PRIOR ART
The present invention is an improvement over the prior art comparator circuit disclosed in IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 6, pgs. 926-932, Dec., 1979, entitled "Monolithic Expandable 6 Bit 20 MHZ CMOS/SOS A/D Converter" by Andrew G. F. Dingwall. The prior art circuit is shown in FIG. 1, and includes an input circuit 1, a capacitor 4, an inverter circuit 2 and a switching circuit 3.
The input circuit 1 is responsive to a control signal .phi., for selectively supplying either an input signal Ein, or a reference signal Vref, to node 1N. The input circuit 1 includes an input terminal 13, switching circuits 11 and 12, and a reference terminal 14. The input terminal 13 is adapted to receive the input signal Ein, and the reference terminal 14 is adapted to receive the reference signal Vref. The switching circuit 11 is connected between the input terminal 13 and node 1N, and includes a n-channel MOS transistor 111 connected in parallel with a p-channel MOS transistor 112. The switching circuit 12 is connected between the reference terminal 14 and node 1N, and includes a n-channel MOS transistor 121 connected in parallel with a p-channel MOS transistor 122. Each of the gate electrodes of MOS transistors 111 and 122 is adapted to receive the control signal .phi., and each of the gate electrodes of MOS transistors 112 and 121 is adapted to receive the complement .phi. of the control signal.
If the control signal .phi. is "HIGH", for example, 5 volts, its complement e,ovs/.phi./ is "LOW", such as 0 volts. When control signal .phi. is "HIGH", switching circuit 12 is non-conductive, and switching circuit 11 is conductive, thereby allowing only the input signal Ein to flow from input terminal 13 to node 1N through switching circuit 11. When the control signal .phi. is "LOW", the switching circuit 11 is non-conductive, and switching circuit 12 is conductive, thereby allowing only signal Vref to flow to node 1N. In this manner, circuit 1 can be controlled to selectively allow either input signal Ein, or reference signal Vref, to flow to node 1N.
The inverter circuit 2 is connected between node 2N and an output terminal 5, and includes a p-channel MOS transistor 21 connected in series with a n-channel MOS transistor 22. The source electrode of transistor 21 is connected to a supply potential terminal 23 which receives a supply voltage VDD, such as 5 volts. The source electrode of transistor 22 is connected to ground, and each of the gate electrodes of MOS transistors 21 and 22 is connected to node 2N.
Switching circuit 3 is connected between node 2N and the output terminal 5, and includes a n-channel MOS transistor 31 connected in parallel with a p-channel MOS transistor 32. The gate electrode of MOS transistor 32 is adapted to receive control signal .phi., and the gate electrode of n-channel transistor 31 is adapted to receive the complement e,ovs/.phi./ of the control signal.
FIG. 2 shows a graph of the input-output characteristics of the inverter circuit 2. The graph contains a horizontal axis which indicates the input voltage of inverter circuit 2, a first vertical axis which indicates the output voltage of the inverter circuit 2, and a second vertical axis which indicates the penetrative current of the inverter circuit 2. The penetrative current is defined as that current which flows from supply potential terminal 23 to ground through transistors 21 and 22. In FIG. 2, a curved line S1 shows the relationship between the output voltage to the input voltage of the inverter circuit, and a curved line S3 shows the relationship of the penetrative current to the input voltage of the inverter circuit. The graph further includes a reference line S2 drawn from point zero (0 ) through point P. Point P on the graph represents the point where the input and output voltage of the inverter circuit 2 are each equal to a balance voltage Vbal.
The operation of the comparator circuit will now be described in detail below with reference to FIGS. 1 and 2.
Initially, control signal .phi. is "LOW", thereby causing switching circuit 11 to be non-conductive, and switching circuits 3 and 12 to be conductive. Switching circuit 3 acts to "equalize" the voltage between the input and output of inverter circuit 2. More specifically, since switching circuit 3 is conductive, the potential at node 2N is equal to the potential at the output terminal 5. In FIG. 2, the potential at node 2N, which is the input of inverter circuit 2, is equal to the potential at the output terminal 5, which is the output of inverter circuit 2, when the potentials at node 2N and at the output terminal 5 are each equal to voltage Vbal. Further, since switching circuit 12 is conductive, voltage signal Vref is applied to node 1N through switching circuit 12, and voltage signal Vbal is applied to node 2N as described above. As a result, capacitor 4, which is connected between nodes 1N and 2N, is charged up to a voltage equal to (Vref-Vbal).
Now that the voltage Vout at output terminal 5 is equal to Vbal, the logic state of the control signals are reversed for sampling the input voltage signal Ein. More specifically, control signal .phi. becomes "HIGH", and its complement e,ovs/.phi./ becomes "LOW". Since control signal .phi. is "HIGH", switching circuit 11 becomes conductive, and switching circuits 3 and 12 each become non-conductive. As switching circuit 11 becomes conductive, input signal Ein flows from terminal 13 to node 1N through switching circuit 11. As a result, the voltage across capacitor 4 changes from (Vref-Vbal) to a voltage equal to (Ein-Vbal). If the input voltage Ein is higher than the reference voltage Vref, the change in the input voltage to the inverter 2 is positive, thereby causing the output voltage of inverter circuit 2 to drop to near 0 volts from the point P shown in FIG. 2. Alternatively, if the input voltage Vin is lower than the reference voltage Vref, the change of the input voltage to inverter circuit 2 is negative, thereby causing the output voltage of inverter circuit 2 to increase to voltage VDD from the point P shown in FIG. 2. In this manner, the comparator circuit of FIG. 1 can compare the input voltage Vin with the reference voltage Vref, and determine whether Vin is larger, (output of the inverter is 0) or smaller, (output of the inverter is VDD) than the reference voltage Vref.
As described in the IEEE Journal article referenced above, a high speed A/D converter can be constructed having sixty-four of the above prior art comparator circuits connected in parallel. In such an A/D converter, when switching circuit 3 is turned ON, input node 2N and output terminal 5 of the inverter 2 are connected electrically, resulting in each of the voltages at node 2N and at terminal 5 becoming equal to the balance voltage Vbal, as indicated by point P of FIG. 2. However, when switching circuit 3 is conductive, the p-channel MOS transistor 21 and the n-channel MOS transistor 22 of inverter circuit 2 are each ON, thereby causing the penetrative current of the inverter to be at a maximum as shown by curve S3 at point P. As a result, an A/D converter circuit constructed having a plurality of the prior art comparator circuits will consume a large amount of power at the time when the input and output of the inverter circuit 2 are each equal to balance voltage Vbal.
One solution to the above power consumption problem is to make the on-resistance of transistors 21 and 22 relatively large. By increasing the on-resistance of transistors 21 and 22, the penetrative current flowing through these transistors would be decreased. However, this solution introduces new problems into the A/D converter circuit since an increase in on-resistance of transistors 21 and 22 will decrease the driving capacity of the inverter circuit 2. More specifically, the present magnitude of the output voltage of the inverter circuit 2 of FIG. 1 is always relatively close to the balance voltage Vbal, thereby requiring only a minimal equalizing period for the output voltage to equal voltage Vbal. If the on-resistance of transistors 21 and 22 of the inverter circuit 2 is increased, the magnitude of the output voltage of the inverter will become relatively far from the balance voltage Vbal. Since the output voltage of the inverter circuit 2 is required to be equal to the balance voltage Vbal for comparing the input voltage Ein with the reference voltage Vref, the time period for equalizing the input and output voltages of the inverter 2 would be longer. In particular the equalizing time will be significantly longer when the output voltage of the inverter is far from the balance voltage Vbal. This longer equalizing time period necessarily lowers the operating speed of the circuit.
As is apparent from the problems associated with the comparator circuit of FIG. 1 (e.g. excessive power consumption and diminished operating speed), and more particularly, with an A/D converter circuit having a number of the comparator circuits, there remains a continuing need for an improved comparator circuit which consumes a relatively small amount of power, and which operates at a high rate of speed.